Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2

Job Description

We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, timing closure, and advanced-node design challenges.

Key Responsibilities

Own and execute the end-to-end physical design flow from synthesized netlist to GDSII for high-performance, low-power SoC designs. Perform floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, and timing closure. Optimize Power, Performance, and Area (PPA) for advanced-node designs, particularly at 2nm and 3nm. Analyze and resolve setup/hold timing violations, congestion, signal integrity, crosstalk, IR drop, and electromigration (EM) issues. Work on advanced semiconductor process nodes, including 2nm, 3nm, 4nm, and 5nm technologies. Use industry-standard physical design and signoff tools, including Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, and Calibre. Collaborate with RTL, synthesis, STA, physical verification, and design teams to achieve performance, power, and area targets. Required Skills 5 10 years of hands-on Physical Design / VLSI implementation experience. Strong experience with Cadence Innovus. Hands-on experience with TSMC 3nm and/or 2nm process technology is highly preferred. Experience with advanced nodes such as 4nm and 5nm is also relevant. Strong understanding of the complete Netlist-to-GDSII physical design flow. Expertise in floorplanning, placement, CTS, routing, and timing closure. Experience with PPA optimization, static timing analysis (STA), IR drop, EM, and crosstalk analysis. Working knowledge of Synopsys Fusion Compiler, PrimeTime, and Calibre. Preferred Background GPU, high-performance computing (HPC), or complex SoC physical design experience. Experience meeting aggressive power, performance, and area targets at advanced process nodes. Experience debugging complex physical implementation and signoff issues.