Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values

• Be Fearless:Unmute yourself. Test boundaries and get proven right.
• Remain Adaptable:Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
• Educate Your Ego:Selflessly collaborate towards our shared purpose.

About the role:

We are looking for an experienced and highly motivatedLeadVector ComputeArchitect to lead the architecture definition and technical direction forBolt’snext-generationGPUs. The ideal candidate will have strongexpertiseindataparallelcomputeunitarchitecture development, performance modeling,data pathintegration, and cross-functional collaboration across hardware, software, and systemsteams.

This role involves defining scalable and high-performance architectures for advancedcomputeworkloadsincludinggraphics,HPC,andsystem management.

What you'll do:

• Define data parallel microarchitecture satisfying ISA constraints.

• Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability.

• Develop and review system architecture specifications, interface definitions, and microarchitecture requirements.

• Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle.

• Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC or similar modeling environments.

• Define memory hierarchy, coherency architecture, and cache structures.

• Work closely with verification teams to define architectural test plans and validation strategies.

• Support silicon bring-up, debug, performance tuning, and post-silicon optimization.

• Contribute to long-term technology and product roadmap planning.

Qualifications:

• Strong understanding of modern data parallel microarchitectures and subsystem integration.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 6+ years of experience in modern data parallel microarchitecture including:

• Workload characterization and profiling

• Performance modeling

• Out-of-order data dependency and control

• Utilization / occupancy optimization

• High-performance architecture design techniques

Experience with one or more of the following:

• CPU/GPU/NPU architectures

• NoC/interconnect architectures

• Cache coherency protocols (CHI/ACE/CXL)

• High-speed interfaces (PCIe, UCIe, Ethernet)

• Memory systems (DDR, LPDDR, HBM, GDDR)

• Power,performance,andareaoptimization

• Strong knowledge of RTL development and verification methodologies.

• Experience with architecture modeling and performance analysis tools.

• Familiarity with firmware/software interaction in complex SoC systems.

• Excellent problem-solving, communication, and leadership skills.

Compensation Range: Market rate for Taiwan. The final offer may vary based on qualifications, experience, and location.

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.

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